The present invention relates to static memory cells using a pair of cross-coupled NPN transistors.
A typical prior art static random access memory (RAM) memory cell is shown in FIG. 1. A word line driver circuit 10 is coupled to a word line 12 which is coupled to a plurality of memory cells of which two memory cells 14 and 16, are shown. Each memory cell coupled to a particular word line is also coupled to a different pair of bit lines. For instance, memory cell 14 is coupled to a bit line 18 and an inverse bit line 20.
Each memory cell in the array has the structure of memory cell 14. In a typical array there will be thousands of such cells. Each cell includes a pair of cross-coupled NPN transistors 22, 24 with the collector of transistor 22 coupled to the base of transistor 24 and the collector of transistor 24 coupled to the base of transistor 22. A first emitter of each of transistors 22, 24 is coupled to bit lines 18 and 20, respectively, and a second emitter is coupled to a current source 26 which provides the standby current for all the cells of a word. The collectors of transistors 22, 24 are coupled to load resistors 28, 30, respectively.
In operation, one of transistors 22, 24 is normally conducting and the other is cut-off. In the standby mode, if transistor 22 is the one conducting, its collector will be at a voltage equal to the value of load resistor 28 times the standby current below the voltage at word line 12. The base of transistor 24 will be at the same voltage. Because the emitter of transistor 24 is at the same voltage as the emitter of transistor 22, this lower base voltage results in transistor 24 being cut-off.
To read the cell, the voltage of word line 12 is raised, thus forcing more current through resistor 28 and transistor 22 and out the second emitter of transistor 22 onto bit line 18, where it is detected. In order to write into memory cell 14, bit line 18 is raised relative to the most negative supply and bit line 20 is lowered relative to the most negative supply, thereby turning on transistor 24. The voltage at the collector of transistor 24 falls, turning off transistor 22. The voltage at the collector of transistor 22 rises, pulling up the base of transistor 24, which in turn pulls up bit line 20 to reflect the opposite state of the cell.
In order to reduce the time delay required for changing the state of the cell or reading the data last written into the cell, the charge stored in the cell must be minimized. The magnitude of the charge stored in the cell is determined by the amount of forward bias across the base-collector junction of transistor 22. This is currently done by limiting the voltage drop across load resistor 28 by means of a diode 38, thereby limiting the forward bias on the collector-base junction of transistor 22. A standard diode may still have a voltage drop of approximately 800 millivolts (mV), which will still saturate the memory cell transistor, although the amount of saturation is limited. By using a Schottky diode, the voltage drop can be limited to approximately 600 millivolts, so that the memory cell transistor is only slightly saturated.
If diode 38 is formed by a relatively large junction consisting of an extended base region and buried layer, its effectiveness at limiting stored charge is determined by its area. If diode 38 is a Schottky diode, it introduces the undesirable complications of requiring the reference level that senses the state of the cell to have a Schottky dependency over temperature and manufacturing variability. This increases the manufacturing costs.
Another important design consideration is the noise margin of word line 12. A large differential between the high and low voltage levels on word line 12 is desired to increase the noise margin. The read current through the load resistors and clamping diodes will pull down the high voltage level of word line 12 when it is selected, lowering the noise margin. It is thus desirable to limit the read current.